Emulation systems are used to verify electronic circuit designs prior to fabrication as chips or manufacture as electronic systems. Typical emulation systems utilize either interconnected programmable logic chips or interconnected processor chips. Examples of hardware logic emulation systems using programmable logic devices can be seen in, for example, U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191. U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191 are incorporated herein by reference. Examples of hardware logic emulation systems using processor chips can be seen in, for example, U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030. U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030 are incorporated herein by reference.
The design under verification (or test) (“DUV”) is usually provided in the form of a netlist description of the design. The netlist may have been derived from many sources, including from a hardware description language. A netlist description (or “netlist”, as it is referred to by those of ordinary skill in the art) is a description of the circuit's components and electrical interconnections between the components. The components include all those circuit elements necessary for implementing a logic circuit, such as combinational logic (e.g., gates) and sequential logic (e.g., flip-flops and latches). In prior art emulation systems, the netlist is compiled such that it is placed in a form that can be used by the emulation system. In an FPGA-based emulator, the DUV is compiled into a form that allows the logic gates (both sequential and combinational) to be implemented in the FPGAs. In a processor-based emulation system, the DUV is compiled into a series of statements that will be executed by the processors on the processor chips. No logic is implemented into these processors.
Conventional hardware emulation systems include target interface systems for coupling with one or more user testbenches and/or target systems. A “target system” is, generally speaking, the actual operating environment that the DUV, once manufactured, will be installed. Thus, the target system for a microprocessor DUV can be a personal computer. A “testbench,” in this context, is an application that may apply a set of stimuli (such as a test vector) to a model to produce a set of information used in analyzing the timing or performance of a system block. The target interface systems of these hardware emulation systems suffer from several limitations. For example, the input/output (I/O) technologies employed by such target interface systems are not suitable for supporting differential signaling technologies. Connection to a differential target system requires the use of additional technology conversion hardware, which generally must be custom made. The design under test thereby is required to expose a single logical signal as a primary I/O (as opposed to possibly two nets), requiring manual intervention into the netlist of the design.
Other disadvantages of the target interface systems of conventional hardware emulation systems include the use of fixed input/output (I/O) technologies. The target interface systems likewise provide limited I/O timing control as well as a limited number of directional signals for bidirectional signals. Further, conventional target interface systems cannot verify the validity of the I/O voltage of the target system and are unable to detect whether the target system is powered on, powered off, or unconnected.
In view of the foregoing, a need exists for an improved hardware emulation system that overcomes the aforementioned obstacles and deficiencies of currently-available hardware emulation systems.
It should be noted that the figures are not drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the preferred embodiments of the present invention. The figures do not describe every aspect of the present invention and do not limit the scope of the invention.